1. Field of the Invention
The invention generally relates to semiconductor based products and more particularly to the fabrication and design of integrated circuit structures.
2. Background of the Invention
A typical integrated circuit consists of a substrate on which devices are formed in and/or on the substrate. Such devices include for example transistors and capacitors that may be interconnected with one another and/or communicate with an external source.
One common approach to making an integrated circuit is to fabricate the circuit as part of a wafer such as a semiconductor wafer on which multiple integrated circuits are formed simultaneously. Fabricating these circuits at the wafer level allows similar circuits to be formed at one time which tends to make the fabrication process more efficient. Once formed the wafer is singulated into individual dies or chips. Currently, single crystal silicon wafers are up to 300 mm or 12 inches in diameter and about 750 microns thick. A 300 mm diameter wafer needs to be about 750 microns thick to avoid problems with breakage during processing and warpage of the wafer.
There are currently applications for semiconductor integrated circuits that require die (device) thickness of substantially less than 750 microns. In order to conserve space in packaging, and to increase memory density in a given area, such as flash memory circuits, an emerging technology is to stack integrated circuits one on top of another. In these situations, it would be beneficial to have circuit thicknesses of less than 100 microns.
Currently, these requirements are being met by processing the circuits using a 750 micron thick wafer and then thinning the unused portion of the silicon wafer to reduce the thickness to a more suitable number of approximately 25 to 100 microns. The thinning technique is typically chemical-mechanical polishing or grinding. The difficulty of the current method is that the thinning is done after the devices and circuits have been processed into the wafer, and thus contributes to loss of circuits through damage to the wafer.
An improved minimum thickness integrated circuit and a method of making a minimum thickness wafer is needed.